Traffic controller timing circuit



Feb. 25, 1969 e. 0. HENDRICKS TRAFFIC CONTROLLER TIMING CIRCUIT Sheet Filed May 12, 1965 I l l l J A K L INVENTOR. GEORGE DONALD HENDRICKS 74.4%, a Bub;

ATTORNEYS Feb. 25, 1969 G. D. HENDRICKS 3,430,069

TRAFFIC CONTROLLER TIMING CIRCUIT Filed May 12. 1965 Sheet g of 2 FROM TO INPUT INVERSE I cmcun' OF OUTPUT I M2 CIRCUIT OF MM! I I l g V V E 22 P O IE(MIN) l k zq f TIME FIG. 3 (PRIOR ART) 3 v v 2 22 P O f I NVENTORL I 2 GEORGE DONALD HENDRlCKS FIG. 4 BY w mw ATTORNEYS United States Patent 3,430,069 TRAFFIC CONTROLLER TIMING CIRCUIT George Donald Hendricks, Campbell Island, 11]., assignor to E. W. Bliss Company, Canton, Ohio, a corporation of Delaware Filed May 12, 1965, Ser. No. 455,062 US. Cl. 307-246 11 Claims Int. Cl. H03k 19/34; G08g 1/095 ABSTRACT OF THE DISCLOSURE A solid state timing circuit adapted to be employed in trafiic controllers, wherein the timing circuit includes a timing capacitor which during each timing cycle of operation is charged with energy for a predetermined time, and is then partially discharged through an electronic control device, such as a unijunction transistor. This circuit further includes a switching circuit connected across the capacitor to completely discharge the capacitor, thereby resetting the timing circuit for a succeeding timing cycle of operation.

This invention is directed toward a trafiic controller and, more particularly, to a traffic controller having an improved static element timing circuit.

The present invention is an improvement of my United States Patent No. 3,072,883, entitled Traflic Controllers Employing Static, Logic Control Elements, assigned to the same assignee of the present invention. Briefly, one trafiic controller described in that patent comprises static, logic control elements for controlling trafiic signals which display go, caution and stop intervals to main street and cross street traffic flow at a trafiic flow intersection. The static control elements take the form of four memory units and four timing units, one memory unit and one timing unit for each of the main street and cross street go and caution intervals. Each memory unit has an ON and an OFF condition, and an input circuit and an output circuit. Each timing unit couples an output circuit of a preceding memory unit with an input circuit of a succeeding memory unit for purposes of timing the ON condition of the preceding memory unit for a predetermined period of time, and then actuating the succeeding memory unit to its ON condition. A circuit connects the output circuit of each memory unit with an input circuit of a preceding memory unit for purposes of actuating the latter to its OFF condition when the former is in its ON condition. The stop intervals need not be timed separately since a circuit is provided to allocate a cross street stop interval during the periods that the controller times main street go and caution intervals and, similarly, a circuit is provided to allocate a main street stop interval during the periods that the controller times cross street go and caution intervals.

The period of a traffic signal cycle is normally in the range of 60 to 100 seconds and during each cycle the trafiic controller described above times four intervals, main street go and caution intervals and cross street go and caution intervals. Thus, each timing unit in the controller will repeat its timing operation as often as 60 times an hour, or 1,440 times a 24 hour work day for a total of 525,600 times a year. To achieve repeat timing reliability, long operating life, and to minimize maintenance, each timing unit should have no moving parts, such as is inherent with the use of relays and electromechanical timers. Preferably, each timing unit should take the form of a static element timing circuit.

A known static element timing circuit takes the form of a unijunction transistor relaxation oscillator circuit, such as that illustrated in Figure 13.18 in General Electrics ICC Transistor Manual, Seventh Eidition. Briefly, that circuit includes: a timing capacitor for charging and discharging energy during each timing cycle of operation; a circuit for charging the capacitor; and, a unijunction transistor having an input circuit connected across the capacitor and an output circuit. The transistor will become forward biased when the value of the voltage charged by the capacitor attains a level equal to the peak point voltage of the transistor, whereupon the capacitor will partially discharge through the input to output circuit of the transistor until the transistor ceases to conduct, which occurs when the voltage across its input circuit, i.e., the voltage across the capacitor, decreases to a certain value which is a characteristic of a unijunction transistor. Hence, upon the completion of a first timing cycle of operation of such a circuit, the timing capacitor will be slightly charged with voltage, requiring less time during the next succeeding timing cycle of operation for the capacitor to charge to a level equal to the peak point voltage of the transistor.

It is important that the time period of each traific interval timed by a traflic controller be the same during the first and all succeeding trafiic signal cycles of operation. For example, municipalities frequently use a plurality of traflic controllers each having the same cycle length period of operation to control trafiic flow within a given area to obtain a desired trafiic flow progression. If the cycle length period of operation is the same for all of the controllers, then the controllers should operate together in synchronism. But, if the time period of any traffic interval timed by the timing units of one of the controllers is not the same for the first and all succeeding trafiic cycles of operation, then the cycle length period of operation of that controller will be difi'ernt from that of the other controllers and, thus, all controllers in the system will not operate together in synchronism, resulting in a disruption of tratfic flow progression.

The present invention is directed toward an improved static timing circuit having a timing capacitor which is completely discharged after a cycle of timing operation, and which timing circuit is particularly adapted for use with a static, logic control element trafiic controller, as well as other uses, and wherein the noted disadvantages, and others, of previous timing circuits are overcome.

The present invention contemplates a static, logic control element traffic controller similar to that disclosed in my Patent No. 3,072,883, wherein each timing unit includes a RC timing circuit having a timing capacitor which during each timing cycle of operation is charged with energy for a predetermined period of time, and is then partially discharged through an electronic control device, such as a unijunction transistor. In accordance with the present invention, a static switch is connected across the capacitor, which switch has a normal first condition presenting a high impedance to current flow therethrough, and a second condition presenting a low impedance to current flow therethrough, and an actuating circuit serves to actuate the static switch to its second condition so that the timing capacitor will completely discharge therethrough, thereby resetting the timing circuit for a succeeding timing cycle of operation.

In accordance with another aspect of the invention, an improved static element relaxation oscillator timing circuit is provided having a timing capacitor and a static switch actuated after completion of each cycle of timing operation for completely discharging the capacitor.

In accordance with a still further and preferred aspect of the present invention, the static switch takes the form of a transistor having its output circuit connected across the timing capacitor of a unijunction relaxation oscillator timing circuit, and its input circuit coupled to the output circuit of the timing circuit.

The principal object of the present invention is to pro vide an improved static element timing circuit for use with a static, logic element trafiic controller.

Another object of the present invention is to provide an improved RC timing circuit wherein the timing capacitor is completely discharged after a cycle of timing operation.

A still further object of the present invention is to provide a static element unijunction relaxation oscillator timing circuit wherein the timing capacitor completes its dis charge through a static switch upon the completion of a timing cycle of operation.

The invention may take physical form in certain parts and arrangement of parts, a preferred embodiment of which will be described in detail in the specification and illustrated in the accompanying drawings which are a part hereof, and wherein:

FIGURE 1 is a block diagram of a two phase trafiic controller employing static logic elements;

FIGURE 2 is a schematic circuit diagram of a logic timer module employing the present invention;

FIGURE 3 shows a graphical waveform of voltage versus time illustrating the operation of a conventional unijunction transistor relaxation oscillator; and,

FIGURE 4 shows a graphical waveform of voltage versus time illustrating the operation of the preferred embodiment of the present invention.

Referring now to the drawings wherein the showings are for the purposes of illustrating a preferred embodiment of the invention only, and not for purposes of limit ing same, FIGURE 1 illustrates a two phase, pretimed traflic controller for controlling the time during each traflic signal cycle of operation that traflic intervals are displayed by a main street go signal MSG, a main street caution signal MSC, a cross street go signal CSG, and a cross street caution signal CSC, and is comprised generally of four substantially identical memory modules MM1, MMZ, MM3, and MM4, and four substantially identical timer modules TM1, TM2, TM3, and TM4. Preferably, each of the modules MM1 through MM4 and TM1 through TM4 is a transistor logic circuit adapted to be plugged into a printed circuit card. Whereas the invention is described with reference to a pretimed two phase traffic controller, it is not limited to same and may be used with other traflic controllers such as a two or three or more phase semi-actuated or fully actuated controller.

Each of the memory modules MM1 through MM4 includes two NOR circuits connected together as a bistable multivibrator and each timer module TM1 through TM4 includes one NOR circuit and one static element timer circuit. To facilitate the understanding of this invention, each of these circuits is briefly explained below.

NOR CIRCUIT.This is a single stage gate having two or more input circuits and one output circuit. A positive output potential signal, known as a (1) signal, is present at its output circuit so long as all of its input circuits receive a ground potential signal, known as a signal. If any of its input circuits receive a (l) signal, a (0) signal will be present at its output circuit.

TIMER CIRCUIT.This is a static element timing circuit having an input circuit and an output circuit. A (1) output signal is present at its output circuit a predetermined time after a (1) input signal is received at its input circuit.

Timer modules TM1 through TM4 are respectively used to time the traffic intervals displayed by trafiic signals MSG, MSC, CSG, and CSC. Each timer module TM1 through TM4 is preceded and followed by a memory module MM1 through MM4. The memory modules MM1 thorugh MM4 are substantially identical and timer modules TM1 through TM4 are substantially identical and, accordingly, only memory module MM1 and timer 4 module TM1 will be described hereinafter in detail, it being understood that the description applies equally to memory modules MM2 through MM4 and timer modules TM2 through TM4.

Memory module MM1 includes two resistor transistor logic NOR circuits 10 and 12, each having a plurality of input circuits and a plurality of output circuits. The input circuits of NOR circuit 10 and the output circuits of NOR circuit 12 will hereinafter be respectively referred to as the input and output circuits of memory module MM1, and the output circuits of NOR circuit 10, and the input circuits of NOR circuit 12 will hereinafter be respectively referred to as the inverse output and inverse input circuits of memory module MM1. One of the output circuits of memory module MM1 is connected to the main street go signal MSG, another output circuit of module from the output circuit of NOR circuit 12 to the input circuit of NOR circuit 10 to provide a bistable multivibrator circuit, and another output circuit of memory module MM1 is connected to an inverse input circuit of memory module MM4. One of the input circuits of memory module MM1 is connected to a B+ voltage supply source through a normally open, manually operable switch S1 and another input circuit is connected to the output circuit of timer module TM4. One of the inverse output circuits of NOR circuit 10 of memory module MM1 is connected internally of the module to an inverse input circuit of NOR circuit 12, and another inverse output circuit is connected to an input circuit of timer module TM1. The other inverse input circuit of memory module MM1 is connected to an output circuit of memory module MM2. During operation of memory module MM1 a continuous (1) output signal will be present at its output circuits, and a ground potential signal, known as a (0) signal, will be present at its inverse output circuits after a momentary application of a (1) signal to any of its input circuits.

Timer module TM1 includes a resistor transistor logic NOR circuit 14 and a unijunction transistor relaxation oscillator timing circuit 16. The input circuit of timer TM1 is the input circuit of NOR circuit 14 and is connected to the inverse output circuit of its preceding memory module MM1. The output circuit of NOR circuit 14 is connected within timer module TM1 to the input circuit of timing circuit 16. The output circuit of timer module TM1 is the output circuit of timing circuit 16 and is connected to an input circuit of memory module MM2. The timing circuit 16 within each of the timer modules T M1 through TM4 is adjustable so that a different predetermined period of time, as desired, may be timed by the timer modules TM1 through TM4.

Trafi'ic controller operation The operation of the trafiic controller illustrated in FIG- URE 1 commences upon closure of switch S1 which applies B+ positive potential, a (1) signal, to an input circuit of NOR circuit 10 of memory module MM1, which becomes energized. Thus, a (0) signal will be present on the output circuit of NOR circuit 10 (inverse output circuit of memory module MM1), which signal is applied to an input circuit of NOR circuit 12 (inverse input circuit of memory module MM1). A (1) signal will be present on all of the output circuits of memory module MM1 so that a (1) signal is applied to the main street go signal MSG for energizing the signal, thereby displaying a go interval to main street traflic flow. A (1) signal will be applied within the memory module MM1 from the output circuit of NOR circuit 12 to the input circuit of NOR circuit 10 for maintaining memory module MM1 energized even if switch S1 is opened. Also, a (1) signal will be applied from the output circuit of memory module MM1 to the inverse input circuit of memory module MM4 for de-energizing the memory module MM4. When memory module MM4 is de-energized a (0) signal will be present at all of its output circuits, causing the cross street caution signal CSC to be de-energized. A (0') signal will be applied from an inverse output circuit of memory module MM1 to the input circuit of NOR circuit 14 of timer module TM1. Thus, a (1) signal will be present on the output circuit of NOR circuit 14 of timer module TM1, which signal is applied within the module to the input circuit of timing circuit 16. After a predetermined period of time, a (1) output signal will be present on the output circuit of timing circuit 16, which signal is applied to the input circuit of memory module MM2, which becomes energized. Memory module MM2 will, in turn, have a (1) output signal present on its output circuits, and a (1) signal is applied therefrom to an inverse input circuit of memory module MM1 to tie-energize memory module MM1. This causes a (0) signal to be applied to main street go signal MSG to de-energize the main street go signal.

Memory module MM2 also applies a (1) output signal to the main street caution signal MSC for energizing the signal, thereby displaying a caution inerval to main street traffic flow. A (0) output signal will be present on the output circuits of memory module MM2 and one of the inverse output circuits applies a (0) signal to the input circuit of timer module TM2. Timer module TM2, in a manner similar to that as described above with respect to timer module TM1, serves after a predetermined period of time to apply a (1) output signal to an input circuit of memory module MM3, which becomes energized. A (1) output signal will be present on all of the output circuits of memory module MM3, and a (1) signal is applied from one of the output circuits to an inverse input circuit of memory module MM2, thereby de-energizing memory module MM2 and in turn tie-energizing the main street go signal MSG.

Memory module MM3 also applies a (1) output signal to its cross street go signal CSG for energizing the signal, thereby displaying a go signal to cross street traflic flow. Memory module MM3 also applies a (0) signal from its inverse output to the input circuit of timer module TM3 which after a predetermined period of time serves to apply a (1) output signal to an input circuit of memory module MM4, which becomes energized. Memory module MM4 when energized will apply a (1) output signal from one of its output circuits to an inverse input circuit of memory module MM3, thereby de-energizing memory module MM3 and, in turn, de-energizing the cross street go signal CSG.

Memory module MM4 also applies a (1) output signal from one of its output circuits to the cross street caution signal CSC for energizing the signal, thereby displaying a caution interval to cross street traiiic flow. Memory module MM4 also applies a (0) signal from its inverse output circuit to the input circuit of timer module TM4, which, after a perdetermined period of time, serves to apply a (1) output signal to an input circuit of memory module MM1, which becomes energized. Memory module MM1, when energized, applies a (1) output signal from its output circuit to the inverse input circuit of memory module MM4, thereby de-energizing memory module MM4 and in turn de-energizing the cross street caution signal CSC. The tratfic controller has now completed one cycle of operaion and all suceeding cycles of operation are substantially the same as described above.

Timer modules The timer modules TM1 through TM4 are substantially identical and, in accordance with the present invention, each takes the form, for example, as module TM1, schematically illustrated in FIGURE 2, and which generally includes a resistor transistor logic NOR circuit 14 and a unijunction relaxation oscillator timing circuit 16. Timing circuit 16 includes a unijunction transistor 18 having an emitter 20, a first base B1, and a second base B2. The input circuit of transistor 18 is taken between ground G and the emitter 20 and is connected across a timing capacitor 22. Capacitor 22 is connected in series with a capacitor charging circuit including an adjustable timing resistor 24 and a resistor 26, within NOR circuit 14, connected together in series between ground G and a B+ voltage supply source, also located in NOR circuit 14. Base B2 of transistor 18 is connected to the B+ voltage supply source through a reserve bias circuit including resistor 28. Base B1 is connected to ground G through load resistor 30. A diode 32, poled as shown in FIGURE 2, is connected across timing resistor 24 for purposes of facilitating complete discharge of capacitor 22 after a cycle of timing operation, as will be appreciated from the description of operation which follows below. The output circuit of transistor 18 is taken between ground G and base B1 across load resistor 30 and is connected to the input circuit of memory module MM2.

The unijunction transistor oscillator circuit described thus far, with the exception of the diode 32, is similar to that as illustrated in Figure 13.18 of General Electrics Transistor Manual, Seventh Edition. During each cycle of timing operation of the circuit illustrated in FIGURE 2, capacitor 22 will charge exponentially, as illustrated by wave form V in FIGURE 3, toward the value of the B+ voltage supply source at a rate according to 3. RC time constant determined by the values of resistors 24 and 26 and capacitor 22. The positive reverse bias voltage on base B2 of transistor 18 will be steady state, as illustrated by the waveform V in FIGURE 3. As the voltage stored by the timing capacitor 22 with reference to ground G increases in magnitude, the voltage appearing on emitter 20 of transistor 18 with reference to ground G will also increase. When the magnitude of the voltage stored by the capacitor 22 attains a level equal to the peak point voltage, illustrated by the waveform V in FIGURE 3, of nnijunction transistor 18, the emitter 20 will become forward biased and the dynamic resistance between emitter 20 and base B1 will drop to an exceedingly small value. The capacitor 22 will then begin to discharge through a discharge circuit including the emitter 20 and base B1 of transistor 18, through the load resistor 30 to ground G. Due to the characteristics of unijunction transistor 1'8, the timing capacitor 22 will not completely discharge to ground potential since the transistor will cease to conduct when the emitter voltage decreases to a value, characteristic of a unijunotion transistor, known as V as illustrated in FIGURE 3. Thus, upon the completion of the first timing cycle of operation, the timing capacitor 22 will be slightly charged with a voltage V whereby the next succeeding timing cycle will begin operation with capacitor 22 previously charged and accordingly, the stored voltage V will attain a value equal to the peak point voltage V of transistor 18 in slightly less time than that required during the first cycle. With reference to FIGURE 3, it will be noted that the time interval 11 required to forward bias the transistor 18 during a first timing cycle of operation is slightly greater than time interval :2 required during the next succeeding timing cycle of operation.

Further in accordance with the present invention, a static switch, preferably taking the form of a N-PN transistor 34, is provided in the NOR circuit 14 of timing module TM1 for purposes of facilitating complete discharge of timing capacitor 22 to thereby reset capacitor 22 after a timing cycle of operation so that each time interval timed by timing capacitor 22 will be the same. Transistor 34 has a collector 36 connected to the B+ voltage supply source through resistor 26, an emitter 38 connected to ground G, and a base 40. Base 40 is connected to an inverse output circuit of memory module MM1 through a current limiting resistor 42 and is also connected to a B- voltage supply source through a bias resistor 44.

Operation of timer modules When the time module TM1 is not performing a timing operation, a positive potential, i.e., a (1) signal, is applied to the base 40 of transistor 34 from an inverse output circuit of memory module MM1. This positive potential is taken from a B+ voltage supply source through current limiting resistor 42, which exhibits a resistance approximately 6 of that of bias resistor 44. Accordingly, the resultant potential on base 40 will be a positive potential with respect to emitter 38 and transistor 34 will be forward biased and conductive. When transistor 34 is forward biased it will present a low impedance to current flow therethrough, and, hence, current will fiow from the 13+ voltage supply source through resistor 26 and thence through the collector 36 to emitter 38 of transistor 34 to ground G. Due to the low impedance of transistor 34 when it is forward biased, substantially no current will flow through timing resistor 24 and timing capacitor 22 to ground G, since this circuit will present a much higher impedance to current flow therethrou gh than will transistor 34. Accordingly, timing circuit 16 will be de-en ergized.

When the output signal of the inverse output circuit of memory module MM 1 is a ground potential signal, i.e., a signal, the resultant potential appearing on base 40 of transistor 34 with respect to ground G will be a negative potential. Accordingly, transistor 34 will be reverse biased and nonconductive, presenting a very high impedance to current flow therethrough. During this condition current will flow from the B+ voltage supply source through resistor 26, and will bypass transistor 34 and flow through timing resistor 24 to charge timing capacitor 22. After a predetermined period of time according to a time constant determined by the values of resistor 26, timing resistor 24 and capacitor 22, the voltage stored by capacitor 22 and, hence, the voltage appearing on emitter 20 of transistor 18 will respect to ground G, will attain a level equal to the peak point voltage V of transistor 18. Transistor 18 will then become forward biased and conductive whereby capacitor 22 will partially discharge through emitter 20 to base B1 of transistor 18 and thereby develop a positive potential signal, i.e., a (1) signal, across load resistor 30 with respect to ground G, which signal is applied to an input circuit of memory module MM2. With reference to FIGURE 1, it Will be noted that when a ('1) signal is applied to the input circuit of memory module MM'2, memory module MM2 will in turn apply a (1) signal to the inverse input circuit of memory module MM1. When memory module MMl receives a (1) signal at its inverse input circuit, it will become deenergized and apply a (1) signal from its inverse output circuit to the input circuit of timer module TMII, i.'e., it applies a B+ potential signal to the base 40 of transistor 34 through resistor 42. Thus, transistor 34 will become forward biased presenting a low impedance to current flow therethrough. Timing capacitor 22 which, with reference to FIGURE 3, does not completely discharge through transistor 18, will then rapidly complete its discharge through a low impedance circuit including diode 32 and the collector 36 to emitter 38 of transistor 34 to ground G. It will be appreciated from the foregoing description that capacitor 22 will be completely discharged upon the completion of each timing cycle of operation so that with, reference to FIGURE 4, the timed interval 11 of a first timing cycle of operation will be the same as the time interval t2 of a succeeding timing cycle of operation.

in accordance with a preferred embodiment of the invention, the values and types of various components illustrated in FIGURE 2 are found in Table I.

TAB-LE I Component: Component value of type Unijunction transistor 18 2N49'1 Timing capacitor 22 microfarads 120 Timing resistor 24 kilohms 150 Resistor 26 do 3.9 Load resistor 30 ohms 330 Reverse bias resistor 28 do 470 8 TABLE I.--Continued B-lvoltage supply source volts direct current +20 B voltage supply source do 20 Although the invention has been shown in connection with a preferred embodiment, it will be readily apparent to those skilled in the art that various changes in form and arrangement of parts may be made to suit requirements without departing from the spirit and scope of the invention as defined by the appended claims.

I claim:

1. A traffic controller for controlling the display of go and caution intervals to main street and cross street trafiic flow at a traffic flow intersection, comprising:

a plurality of logic memory means one each for main street and cross street go and caution intervals, each said memory means having an input and an output and having a first condition and a second condition;

a like plurality of timing means each coupling the output of a preceding memory means with the input of a succeeding memory means for timing the first condition of said preceding memory means for a predetermined period of time and then actuating said succeeding memory means to its said first condition; and,

coupling means for also coupling the output of a said succeeding memory means with the input of a said preceding memory means for actuating a said preceding memory means to its said second condition when the said succeeding memory means is in its first condition;

each said timing means including a RC timing circuit having a timing capacitor which is charged with energy for a said predetermined period of time, an electronic control device through which said capacitor partially discharges at the end of said predetermined period of time, static switching means connected across said capacitor and having a normal first condition presenting a high impedance to current flow therethrough and a second condition presenting a low impedance to current flow therethrough, and means for actuating said static switching means to its second condition so that said timing capacitor will completely discharge therethrough to reset said timing means.

2. A trafiic controller as set forth in claim 1, wherein said static switching means of each timing means includes a transistor having an output circuit connected across said capacitor and an input circuit coupled to an output circuit of said electronic control device.

3. A trafiic controller as set forth in claim 1, wherein the electronic control device and static switching means of each timing means respectively take the form of a unijunction transistor and a resistor transistor logic NOR circuit, said NOR circuit having an output circuit connected to an input circuit of .said unijunction transistor and an input circuit coupled with an output circuit of said unijunction transistor in such a manner that the transistor of said NOR circuit will be forward biased presenting low impedance to current flow therethrough when said unijunction transistor becomes conductive.

4. A trafiic controller as set forth in claim 3, wherein the input circuit of said NOR circuit is coupled to the output circuit of said unijunction transistor through the next succeeding and next preceding memory means.

5. In a timing circuit including a unijunction transistor having a first base, a second base and an emitter; said emitter and second base connected to a source of positive direct current voltage through a reverse bias resistor and a timing resistor, respectively; a timing capacitor connected on one side to said emitter and on the other side to said first base through a load resistor;

a NPN transistor means having an emitter and a collector and a base, said NPN transistor means having its collector connected to said one side of said capacitor through said timing resistor and its emitter connected to said other side of said timing capacitor;

a diode connected across said timing resistor in such a manner to present a high impedance relative to said timing resistor to current flow from said voltage source to said timing capacitor and a low impedance relative to said timing resistor to current flow from said capacitor to said unijunction transistor, whereby after applying voltage from said voltage source to said timing circuit said timing capacitor will charge toward the value of said source until the value of the voltage stored attains a level equal to the peak point voltage of the unijunction transistor whereupon said unijunction transistor will be conductive and said timing capacitor will partially discharge through the emitter said unijunction transistor to its said first base to develop a positive voltage pulse across said load resistor; and

a bistable multivibrator means having a normal first condition and a second condition; said multivibrator means being connected to said load resistor in such a manner that when a said positive voltage pulse is developed across said load resistor said multivibrator means changes from said first condition to said second condition; said NPN transistor means being connected to and responsive to said multivibrator means in such a manner that when said multivibrator means is in said second condition said transistor means will be forward biased and present along with said diode a low impedance discharge path through which said timing capacitor will completely discharge.

6. In a timing circuit including a timing capacitor for charging and discharging energy during each timing cycle of operation; means for charging said capacitor; and, an electronic control device having an input circuit connected across said capacitor and an output circuit, said device being conductive when a predetermined level of energy is charged by said capacitor whereupon said capacitor partially discharges through the input to output circuit of said device until said device ceases to conduct thereby providing an output signal; the improvement in means for substantially completely discharging said capacitor comprising:

a bistable multivibrator means having a first condition and a second condition, said multivibrator means being responsive to a said output signal of said output circuit to be actuated to the second condition; and circuit means connecting said multivibrator means to said capacitor in such a manner that when said multivibrator means is in said second condition a discharge path is provided for said capacitor so that said timing capacitor will completely discharge thereby resetting said timing circuit for a succeeding timing cycle of operation; said bistable multivibrator means has an inverse input means for receiving a said output signal thereby changing said multivibrator from said first condition to said second condition.

7. The improvement as set forth in claim 6 wherein said circuit means includes a static switching means connected across said capacitor, said switching means being connected to and controlled by said multivibrator means so that when said multivibrator means is in its second condition a low impedance path is provided across said capacitor thereby completely discharging said capacitor.

8. In a timing circuit as set forth in claim 7 wherein said static switching means is a transistor means having an output circuit connected across said timing capacitor and an input circuit connected to said multivibrator.

9. The improvement as set forth in claim 8 wherein said transistor means is saturated into conduction when a said output signal is provided by said output circuit of said device thereby completely discharging said capacitor.

10. A trafiic control system including:

main street go and caution lamps and cross street g0 and caution lamps;

solid state means for sequentially energizing said main street go lamp, said main street caution lamp, said cross street go lamp and said cross street caution lamp;

solid state timing means coupled to said sequentially energizing means for controlling the time duration that each said lamp is energized;

said timing means including a timing capacitor for charging and discharging energy during each timing cycle of operation; means for charging said capacitor for timing the duration that a said lamp is energized; an electronic control device having an input circuit connected across said capacitor and an output circuit, said device being conductive when a predetermined level of energy is charged by said capacitor whereupon said capacitor partially discharges through the input to output circuit of said device until said device ceases to conduct thereby providing an output signal;

static switching means connected across said capacitor and having a normal first condition presenting a high impedance to current fiow therethrough and a second condition presenting a low impedance to current flow therethrough; and,

means coupled to said output circuit of said control device for actuating said static switching means to its second condition in response to said output signal so that said timing capacitor will completely discharge thereby resetting said timing circuit for a succeeding timing cycle of operation for controlling the duration that a said lamp is energized.

11. A trafiic controller as set forth in claim 10 wherein said means for actuating said static switching means is a bistable multivibrator means having a first condition and a second condition, said multivibrator means being responsive to a said output signal of said output circuit to be actuated to the second condition; and circuit means conmeeting said multivibrator to said capacitor in such a manner that when said multivibrator means is in said second condition a discharge path is provided for said capacitor so that said timing capacitor will completely discharge thereby resetting said timing circuit for a succeeding timing cycle of operation.

References Cited UNITED STATES PATENTS 1/ 1962 Zrubek 307-885 1/ 1967 McDowell et al 307-885 

